產業實習技能(U108417B)
Course Period：Now ~ Any Time
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Course Intro
Course Plan
http://www.lhu.edu.tw/class_intro/EL/EL23542.htm
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數位電路復習
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Simplified FPGA Architecture
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FPGA原理-1
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FPGA原理-2
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加減乘除電路
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鍵盤掃描
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演算法狀態機
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頻譜儀原理
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1.1 verilog 模組
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1.2 verilog Gate
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1.3 verilog 組合電路(結構)_MUX
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1.4 verilog 組合電路(結構)_MUX_nested
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1.5 verilog 組合電路(結構)_decoder
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1.6 verilog 組合電路(結構)_LUT_1
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1.7 verilog 組合電路(結構)_LUT_2
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1.8 verilog 組合電路(結構)_MUX
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1.9 verilog 組合電路(結構)_unsigned_Arithmatic
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1.10 verilog 組合電路(結構)_signed_Arithmatic
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1.11 verilog 組合電路(結構)_concatenation_rotate
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2.1 verilog 組合電路(行為)_always
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2.2 verilog 組合電路(行為)_if_else_MUX
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2.3 verilog 組合電路(行為)_if_else_nested
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2.4 verilog 組合電路(行為)_case_decoder
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2.5 verilog 組合電路(行為)_case_LUT
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2.6 verilog 組合電路(行為)_case_MUX
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2.7 verilog 組合電路(行為)_Latch
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2.8 verilog 組合電路(行為)_Sequential init
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2.9 verilog 組合電路(行為)_decoder
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2.10 verilog 組合電路(行為)_encoder
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2.11 verilog 組合電路(行為)_priority encoder
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2.12 verilog 組合電路(行為)_case_summary
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2.13 verilog 組合電路(行為)_ALU
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3.1 verilog RTL_Reg
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3.2 verilog RTL_multibit_Reg
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3.3 verilog RTL_blocking
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3.4 verilog RTL_nonblocking
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3.5 verilog RTL_Reg+MUX_1
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3.6 verilog RTL_Reg+MUX_2
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3.7 verilog RTL_DeMUX
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3.8 verilog RTL_counter
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3.9 verilog RTL_counter_with_bounds
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3.10 verilog RTL_up_down_counter
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3.11 verilog RTL_CPU
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3.12 verilog RTL_pipeline_1
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3.12 verilog RTL_pipeline_2
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3.13 verilog RTL_Handshake
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3.14 verilog RTL_GPIO
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4.1 verilog FSM
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4.2 verilog FSM_Automatic seller
Teacher / 闕河立
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